For maintaining the data throughput the two subsystems operating at the two clocks ( say f1 and f2 ) are required to be in the ratio 516 / 512 ( = 129 / 128 ). The clock frequencies are related by the equation f1 = 512 / 516 x f2. Since the maximum baseband bandwidth is 16MHz for Nyquist sampling. Two active low signals of one clock cycle wide and same periodicity are to be generated from f1 and f2 respectively. The relative phase of these two carries should be same whenever th esystem is powered on or reset. The RMS time jitter of the sampling clock is required to be better than 200ps.
The following are the sections comprising the clock generation and distribution system :
1.CIRCUIT OF THE DDS BASED CLOCK DISTRIBUTION SYSTEM
2.PROGRAMMING OF DDS
3.TEST RESULTS
4.FUTURE WORKS